Small multi-cycle RV32I core · Example, read-only. Explore every file, run, and layout.
A small multi-cycle RISC-V (RV32I) core running compiled C, with a placed-and-routed layout. Some stretch goals are still open, which is shown honestly.
How your design is built
Each stage shows the files it used and produced, and who made them. Select a stage to open or protect its files, then rerun just that stage or everything after it. Whether your goals are met is in Evaluation.
AI recommendation: SkyWater 130 nm · HD. You can change the platform and rerun; each platform uses its own libraries and physical-design setup.
Workflow run history
0 saved runs, newest first.
No saved workflow runs yet.
Follow the design, files, and evidence through every tool
Branches show retries and optional checks. Select a step to inspect its recorded inputs, outputs, and tool logs below. Pan and zoom to explore the map.
Project requirements, design choices, assumptions, and process recommendation are saved.
SkyWater 130 nm · HD · one-click flow available
4 RTL files and 2 testbenches in the project.
Ready to compile and run the project testbench.
Waiting for the first simulation result.
Skipped because no failed retry is recorded.
The Yosys runner is currently unavailable on this server.
22 goals saved · behavior checks and measurable tool results.
Generate a current mapped netlist first.
Generate a current mapped netlist before physical design.
The selected runner config does not declare a single literal supply net and positive voltage. SiliconForge will not guess these values.
Antenna checking requires process antenna-rule declarations in the selected platform LEFs. This platform does not currently provide them to the runner.
generated/layout/rv32i_core.openroad.gds
The saved SPEF belongs to an older or incomplete physical-design run. Rerun OpenROAD with the current netlist and matching RC rules.
KLayout runner is currently unavailable on this server.
Magic runner is currently unavailable on this server.
OpenSTA runner is currently unavailable on this server.
Reference netlist: signoff/reference/rv32i_core.post-route.v
signoff/layout_extracted/rv32i_core.spice
Netgen runner is currently unavailable on this server.
The selected SkyWater 130 nm · HD pack has no process-specific ERC driver, device models, power definitions, and CVC configuration. The workflow skips this optional check rather than inventing process rules.
16/22 goals passed · 6 failed.
Available to download at any point. Contains project files and saved evidence; it is not foundry approval.
RTL simulation
A testbench is present. Run it to establish behavioral evidence.
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No output or measurement recorded yet.
Goals and test evidence
reset_starts_at_zeroBehavior: After active-low reset, execution begins at instruction address 0x00000000. resultpassed
reset_starts_at_zero = 1 result; goal passed.
x0_remains_zeroBehavior: Register x0 always reads as zero and writes targeting x0 have no effect. resultpassed
x0_remains_zero = 1 result; goal passed.
word_loads_return_little_endian_valuesBehavior: LB, LBU, LH, LHU, and LW return correctly sign-extended or zero-extended little-endian values. resultpassed
word_loads_return_little_endian_values = 1 result; goal passed.
completion_gpio_signalBehavior: A nonzero word store to GPIO address 0x10000000 asserts done and halts further retirement. resultpassed
completion_gpio_signal = 1 result; goal passed.
done_remains_asserted_after_completionBehavior: done remains asserted and no instruction retires after completion. resultpassed
done_remains_asserted_after_completion = 1 result; goal passed.
testbench_pass= 1 resultpassed
testbench_pass = 1 result; goal passed.
global_route_overflow≤ 0 edgespassed
global_route_overflow = 0 edges; goal passed.
layout_export_complete= 1 resultpassed
layout_export_complete = 1 result; goal passed.
parasitic_extraction_complete= 1 resultpassed
parasitic_extraction_complete = 1 result; goal passed.
antenna_net_violation_count≤ 0 netsfailed
antenna_net_violation_count = 2 nets; goal did not meet its target.
antenna_pin_violation_count≤ 0 pinsfailed
antenna_pin_violation_count = 3 pins; goal did not meet its target.
power_grid_vdd_connected= 1 resultpassed
power_grid_vdd_connected = 1 result; goal passed.
power_grid_vss_connected= 1 resultpassed
power_grid_vss_connected = 1 result; goal passed.
antenna_check_complete= 1 resultpassed
antenna_check_complete = 1 result; goal passed.
drc_top_level_violation_count≤ 0 violationsfailed
drc_top_level_violation_count = 70 violations; goal did not meet its target.
drc_violation_count≤ 0 violationsfailed
drc_violation_count = 117692 violations; goal did not meet its target.
drc_cell_internal_violation_count≤ 0 violationspassed
drc_cell_internal_violation_count = 0 violations; goal passed.
layout_extraction_complete= 1 resultpassed
layout_extraction_complete = 1 result; goal passed.
worst_slack_ns≥ 0 nsfailed
worst_slack_ns = -17.072872 ns; goal did not meet its target.
drc_macro_internal_violation_count≤ 0 violationsfailed
drc_macro_internal_violation_count = 117622 violations; goal did not meet its target.
power_grid_vdd_unconnected_instances≤ 0 instancespassed
power_grid_vdd_unconnected_instances = 0 instances; goal passed.
power_grid_vss_unconnected_instances≤ 0 instancespassed
power_grid_vss_unconnected_instances = 0 instances; goal passed.