Minimal synchronous counter · Example, read-only. Explore every file, run, and layout.
A minimal synchronous counter taken all the way from RTL to a routed, DRC- and LVS-clean layout. The best place to start.
How your design is built
Each stage shows the files it used and produced, and who made them. Select a stage to open or protect its files, then rerun just that stage or everything after it. Whether your goals are met is in Evaluation.
AI recommendation: SkyWater 130 nm · HS. You can change the platform and rerun; each platform uses its own libraries and physical-design setup.
Workflow run history
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Follow the design, files, and evidence through every tool
Branches show retries and optional checks. Select a step to inspect its recorded inputs, outputs, and tool logs below. Pan and zoom to explore the map.
Project requirements, design choices, assumptions, and process recommendation are saved.
SkyWater 130 nm · HS · one-click flow available
2 RTL files and 1 testbench in the project.
Ready to compile and run the project testbench.
Waiting for the first simulation result.
Skipped because no failed retry is recorded.
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22 goals saved · behavior checks and measurable tool results.
Generate a current mapped netlist first.
Generate a current mapped netlist before physical design.
The selected runner config does not declare a single literal supply net and positive voltage. SiliconForge will not guess these values.
Antenna checking requires process antenna-rule declarations in the selected platform LEFs. This platform does not currently provide them to the runner.
generated/layout/synchronous_counter.openroad.gds
The saved SPEF belongs to an older or incomplete physical-design run. Rerun OpenROAD with the current netlist and matching RC rules.
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Reference netlist: signoff/reference/synchronous_counter.post-route.v
signoff/layout_extracted/synchronous_counter.spice
Netgen runner is currently unavailable on this server.
The selected SkyWater 130 nm · HS pack has no process-specific ERC driver, device models, power definitions, and CVC configuration. The workflow skips this optional check rather than inventing process rules.
22/22 goals passed.
Available to download at any point. Contains project files and saved evidence; it is not foundry approval.
RTL simulation
A testbench is present. Run it to establish behavioral evidence.
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No output or measurement recorded yet.
Goals and test evidence
synchronous_resetBehavior: Active-low reset clears the count on the next rising clock edge and does not change the count before that edge resultpassed
synchronous_reset = 1 result; goal passed.
reset_priority_over_enableBehavior: When reset is asserted together with enable, reset clears the count instead of incrementing it resultpassed
reset_priority_over_enable = 1 result; goal passed.
enabled_incrementBehavior: With reset inactive and enable high, the count increments by exactly one on every rising clock edge resultpassed
enabled_increment = 1 result; goal passed.
disabled_holdBehavior: With reset inactive and enable low, the count holds its previous value across rising clock edges resultpassed
disabled_hold = 1 result; goal passed.
modulo_256_rolloverBehavior: With enable high, the count transitions from 255 to 0 on the next rising clock edge resultpassed
modulo_256_rollover = 1 result; goal passed.
testbench_pass= 1 resultpassed
testbench_pass = 1 result; goal passed.
setup_slack_ns≥ 0 nspassed
setup_slack_ns = 9.10509 ns; goal passed.
global_route_overflow≤ 0 edgespassed
global_route_overflow = 0 edges; goal passed.
layout_export_complete= 1 resultpassed
layout_export_complete = 1 result; goal passed.
parasitic_extraction_complete= 1 resultpassed
parasitic_extraction_complete = 1 result; goal passed.
antenna_net_violation_count≤ 0 netspassed
antenna_net_violation_count = 0 nets; goal passed.
antenna_pin_violation_count≤ 0 pinspassed
antenna_pin_violation_count = 0 pins; goal passed.
antenna_check_complete= 1 resultpassed
antenna_check_complete = 1 result; goal passed.
drc_violation_count≤ 0 violationspassed
drc_violation_count = 0 violations; goal passed.
layout_extraction_complete= 1 resultpassed
layout_extraction_complete = 1 result; goal passed.
lvs_match= 1 resultpassed
lvs_match = 1 result; goal passed.
power_grid_vdd_connected= 1 resultpassed
power_grid_vdd_connected = 1 result; goal passed.
power_grid_vdd_unconnected_instances≤ 0 instancespassed
power_grid_vdd_unconnected_instances = 0 instances; goal passed.
power_grid_vss_connected= 1 resultpassed
power_grid_vss_connected = 1 result; goal passed.
power_grid_vss_unconnected_instances≤ 0 instancespassed
power_grid_vss_unconnected_instances = 0 instances; goal passed.
erc_violation_count≤ 0 violationspassed
erc_violation_count = 0 violations; goal passed.
erc_check_complete= 1 resultpassed
erc_check_complete = 1 result; goal passed.